The electrical characteristics and interfacial properties of La2O3/Ge structures under various post-deposition annealing (PDA) conditions are studied. We found that the interfacial Ge oxide layer reduced the Dit, while redundant growth of the oxide led to increment of CET. In order to satisfy small CET and low Dit, appropriate interfacial layer (IL) thickness is assumed to be 1.0-1.5 nm. On the other hand, Ge sub-oxide in the IL caused to increase hysteresis. Instead, by introducing the Ge chemical oxide, an interfacial La-germanate layer formed with PDA at 500 °C in N2, which could reduced both the hysteresis and Dit.
- Interface trap density
- Lanthanum oxide