Improved multi-level control of RRAM using pulse-train programming

Liang Zhao, Hong Yu Chen, Shih Chieh Wu, Zizhen Jiang, Shimeng Yu, Tuo-Hung Hou, H. S.Philip Wong, Yoshio Nishi

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Scopus citations

Abstract

Multi-level cell (MLC) capability in RRAM is attractive for reducing the cost per bit. Based on the filamentary switching mechanisms, we propose a pulse-train programming scheme to achieve reliable and uniform MLC controls without the need of any read-verification operation. By applying the novel scheme to a 3 bit/cell RRAM device, the uniformity of resistance distribution can be improved up to 80%.

Original languageEnglish
Title of host publicationProceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014
PublisherIEEE Computer Society
Pages1-2
Number of pages2
ISBN (Print)9781479922178
DOIs
StatePublished - 28 Apr 2014
Event2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014 - Hsinchu, Taiwan
Duration: 28 Apr 201430 Apr 2014

Publication series

NameProceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014

Conference

Conference2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014
CountryTaiwan
CityHsinchu
Period28/04/1430/04/14

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