Improved device characteristics in charge-trapping-engineered flash memory using high-κ dielectrics

Albert Chin*, S. H. Lin, Chung-Yong Tsai, F. S. Yeh

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

The much shallower trap energy in Si3N4 of [poly-Si]-SiO 2-Si3N4- SiO2-Si (SONOS) charge-trapping flash (CTF) device than conventional poly-Si floating gate flash is the fundamental challenge for CTF device. We have pioneered the high-κ trapping layer CTF memory to increase the trapping energy, where the AlGaN has a large conduction band offset to barrier oxide layer close to conventional poly-Si floating gate. Further device performance improvement is achieved using the novel Charge-Trapping-Engineered Flash (CTEF) device with double barriers for carrier confinements and double shallow-/deep-trapping layers for charge storage. Excellent memory device integrities of large extrapolated 10-year retention of 3.8 V at 150°C, 4 logic levels MLC operation, very fast 100 μs write speed and good 100,000 cycling stress are measured at the same time. These excellent results may allow further down-scaling the flash memory for additional nodes.

Original languageEnglish
Title of host publicationECS Transactions - Physics and Technology of High-k Gate Dielectrics 7
Pages447-455
Number of pages9
Edition6
DOIs
StatePublished - 1 Dec 2009
Event7th International Symposium on High Dielectric Constant Materials and Gate Stacks - 216th Meeting of the Electrochemical Society - Vienna, Austria
Duration: 5 Oct 20097 Oct 2009

Publication series

NameECS Transactions
Number6
Volume25
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Conference

Conference7th International Symposium on High Dielectric Constant Materials and Gate Stacks - 216th Meeting of the Electrochemical Society
CountryAustria
CityVienna
Period5/10/097/10/09

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