Improved annealing process for electroless Pd plating induced crystallization of amorphous silicon

Guo Ren Hu; Tian Jiun Huang; Yew-Chuhg Wu

Improved annealing process for electroless Pd plating induced crystallization of amorphous silicon

Guo Ren Hu, Tian Jiun Huang, Yew-Chuhg Wu^*

^*Corresponding author for this work

Research output: Contribution to journal › Letter › peer-review

1 Scopus citations

Abstract

Electroless Pd plating induced crystallization of amorphous silicon (a-Si) thin films has been proposed for fabricating low-temperature polycrystalline silicon thin film transistors (LTPS TFTs). However, the current crystallization process often leads to poor device performance due to the large amount of Pd-silicide residues in the poly-Si thin films. It was found that the amount of Pd silicide increased with annealing time and temperature. In this study, a two-step annealing process was developed to obtain the appropriate amount of Pd silicide for inducing the crystallization of a-Si. The device characteristics were significantly improved by this two-step process.

Original language	English
Journal	Japanese Journal of Applied Physics, Part 2: Letters
Volume	42
Issue number	8 A
State	Published - 1 Aug 2003

Keywords

Amorphous silicon
Electroless plating and physical vapor deposition
Metal-induced crystallization
Polycrystalline silicon
Thin-film transistor

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title = "Improved annealing process for electroless Pd plating induced crystallization of amorphous silicon",

abstract = "Electroless Pd plating induced crystallization of amorphous silicon (a-Si) thin films has been proposed for fabricating low-temperature polycrystalline silicon thin film transistors (LTPS TFTs). However, the current crystallization process often leads to poor device performance due to the large amount of Pd-silicide residues in the poly-Si thin films. It was found that the amount of Pd silicide increased with annealing time and temperature. In this study, a two-step annealing process was developed to obtain the appropriate amount of Pd silicide for inducing the crystallization of a-Si. The device characteristics were significantly improved by this two-step process.",

keywords = "Amorphous silicon, Electroless plating and physical vapor deposition, Metal-induced crystallization, Polycrystalline silicon, Thin-film transistor",

author = "Hu, {Guo Ren} and Huang, {Tian Jiun} and Yew-Chuhg Wu",

year = "2003",

month = aug,

day = "1",

language = "English",

volume = "42",

journal = "Japanese Journal of Applied Physics",

issn = "0021-4922",

publisher = "Japan Society of Applied Physics",

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T1 - Improved annealing process for electroless Pd plating induced crystallization of amorphous silicon

AU - Hu, Guo Ren

AU - Huang, Tian Jiun

AU - Wu, Yew-Chuhg

PY - 2003/8/1

Y1 - 2003/8/1

N2 - Electroless Pd plating induced crystallization of amorphous silicon (a-Si) thin films has been proposed for fabricating low-temperature polycrystalline silicon thin film transistors (LTPS TFTs). However, the current crystallization process often leads to poor device performance due to the large amount of Pd-silicide residues in the poly-Si thin films. It was found that the amount of Pd silicide increased with annealing time and temperature. In this study, a two-step annealing process was developed to obtain the appropriate amount of Pd silicide for inducing the crystallization of a-Si. The device characteristics were significantly improved by this two-step process.

AB - Electroless Pd plating induced crystallization of amorphous silicon (a-Si) thin films has been proposed for fabricating low-temperature polycrystalline silicon thin film transistors (LTPS TFTs). However, the current crystallization process often leads to poor device performance due to the large amount of Pd-silicide residues in the poly-Si thin films. It was found that the amount of Pd silicide increased with annealing time and temperature. In this study, a two-step annealing process was developed to obtain the appropriate amount of Pd silicide for inducing the crystallization of a-Si. The device characteristics were significantly improved by this two-step process.

KW - Amorphous silicon

KW - Electroless plating and physical vapor deposition

KW - Metal-induced crystallization

KW - Polycrystalline silicon

KW - Thin-film transistor

UR - http://www.scopus.com/inward/record.url?scp=0141457571&partnerID=8YFLogxK

M3 - Letter

AN - SCOPUS:0141457571

VL - 42

JO - Japanese Journal of Applied Physics

JF - Japanese Journal of Applied Physics

SN - 0021-4922

IS - 8 A

ER -