Improved annealing process for electroless Pd plating induced crystallization of amorphous silicon

Guo Ren Hu, Tian Jiun Huang, Yew-Chuhg Wu*

*Corresponding author for this work

Research output: Contribution to journalLetterpeer-review

1 Scopus citations

Abstract

Electroless Pd plating induced crystallization of amorphous silicon (a-Si) thin films has been proposed for fabricating low-temperature polycrystalline silicon thin film transistors (LTPS TFTs). However, the current crystallization process often leads to poor device performance due to the large amount of Pd-silicide residues in the poly-Si thin films. It was found that the amount of Pd silicide increased with annealing time and temperature. In this study, a two-step annealing process was developed to obtain the appropriate amount of Pd silicide for inducing the crystallization of a-Si. The device characteristics were significantly improved by this two-step process.

Original languageEnglish
JournalJapanese Journal of Applied Physics, Part 2: Letters
Volume42
Issue number8 A
StatePublished - 1 Aug 2003

Keywords

  • Amorphous silicon
  • Electroless plating and physical vapor deposition
  • Metal-induced crystallization
  • Polycrystalline silicon
  • Thin-film transistor

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