Improve latch-up immunity by circuit solution

Hui Wen Tsai, Ming-Dou Ker

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

A concept of active guard ring and its corresponding circuit solution to enhance the latch-up immunity of integrated circuits (IC) are proposed and verified in a 0.6-um 5-V CMOS process. By detecting the over-shooting/under-shooting trigger current during latchup current test (I-test), some compensation current generated from on-chip ESD PMOS or NMOS devices through special circuit design can effectively reduce the latchup trigger current that injecting into the core circuit blocks. Therefore, the latchup immunity of I-test with positive or negative trigger current applied at the I/O pins can be significantly improved.

Original languageEnglish
Title of host publicationProceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages527-530
Number of pages4
ISBN (Electronic)9781479999286, 9781479999286
DOIs
StatePublished - 25 Aug 2015
Event22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015 - Hsinchu, Taiwan
Duration: 29 Jun 20152 Jul 2015

Publication series

NameProceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
Volume2015-August

Conference

Conference22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015
CountryTaiwan
CityHsinchu
Period29/06/152/07/15

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