Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability

Wei Hwang, George Diedrich Gristede, Pia Sanda, Shao Y. Wang, David F. Heidel

Research output: Contribution to journalArticlepeer-review

28 Scopus citations

Abstract

This paper presents a fast, low-power, binary carry-lookahead, 64-bit dynamic parallel adder architecture for high-frequency microprocessors. The adder core is composed of evaluate circuits and feedback reset chains implemented by self-resetting CMOS (SRCMOS) circuits with enhanced testability. A new tool, SRCMOS pulse analyzer (SPA), is developed for checking dynamic circuits for proper operation and performance. The nominal propagation delay and power dissipation of the adder were measured to be 1.5 ns (at 22°C with Vdd = 2.5 V) and 300 mW. The adder core size is 1.6 × 0.275 mm2. The process technology used was the 0.5-μm IBM CMOS5X technology with 0.25-μm effective channel length and five layers of metal. The circuit techniques are easily migratable to multigigahertz microprocessor designs.

Original languageEnglish
Pages (from-to)1108-1117
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Volume34
Issue number8
DOIs
StatePublished - 1 Aug 1999

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