Implementation of a hardware-efficient EEG processor for brain monitoring systems

Chiu Kuo Chen*, Ericson Chua, Shao Yen Tseng, Chih Chung Fu, Wai-Chi  Fang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

This paper presents a complexity-efficient architecture for an EEG signal separation processor incorporating ICA with lossless data compression. An average correlation result of 0.9044 is achieved while transmitted EEG data bandwidth and power consumption are reduced by 41.6%. The chip area, operating frequency, and estimated power consumption of the proposed EEG architecture in UMC 90nm SP-HVT CMOS technology are 1,133 by 1,133 um2, up to 32MHz, and approximately 0.70mW at 0.9V supply voltage and 5 MHz operating frequency, respectively.

Original languageEnglish
Title of host publicationProceedings - IEEE International SOC Conference, SOCC 2010
Pages164-168
Number of pages5
DOIs
StatePublished - 1 Dec 2010
Event23rd IEEE International SOC Conference, SOCC 2010 - Las Vegas, NV, United States
Duration: 27 Sep 201029 Sep 2010

Publication series

NameProceedings - IEEE International SOC Conference, SOCC 2010

Conference

Conference23rd IEEE International SOC Conference, SOCC 2010
CountryUnited States
CityLas Vegas, NV
Period27/09/1029/09/10

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  • Cite this

    Chen, C. K., Chua, E., Tseng, S. Y., Fu, C. C., & Fang, W-C. (2010). Implementation of a hardware-efficient EEG processor for brain monitoring systems. In Proceedings - IEEE International SOC Conference, SOCC 2010 (pp. 164-168). [5784735] (Proceedings - IEEE International SOC Conference, SOCC 2010). https://doi.org/10.1109/SOCC.2010.5784735