Impacts of work function variation and line-edge roughness on TFET and FinFET devices and 32-bit CLA circuits

Yin Nien Chen*, Chien Ju Chen, Ming Long Fan, Vita Pi Ho Hu, Pin Su, Ching Te Chuang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

5 Scopus citations

Abstract

In this paper, we analyze the variability of III-V homojunction tunnel FET (TFET) and FinFET devices and 32-bit carry-lookahead adder (CLA) circuit operating in near-threshold region. The impacts of the most severe intrinsic device variations including work function variation (WFV) and fin line-edge roughness (fin LER) on TFET and FinFET device Ion, Ioff, Cg, 32-bit CLA delay and power-delay product (PDP) are investigated and compared using 3D atomistic TCAD mixed-mode Monte-Carlo simulations and HSPICE simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. The results indicate that WFV and fin LER have different impacts on device Ion and Ioff. Besides, at low operating voltage (<0.3 V), the CLA circuit delay and power-delay product (PDP) of TFET are significantly better than FinFET due to its better Ion and Cg,ave and their smaller variability. However, the leakage power of TFET CLA is larger than FinFET CLA due to the worse Ioff variability of TFET devices.

Original languageEnglish
Pages (from-to)101-115
Number of pages15
JournalJournal of Low Power Electronics and Applications
Volume5
Issue number2
DOIs
StatePublished - 21 May 2015

Keywords

  • Carry-lookahead adder (CLA)
  • FinFET
  • Line-edge-roughness (LER)
  • Tunnel FET (TFET)
  • Work function variation (WFV)

Fingerprint Dive into the research topics of 'Impacts of work function variation and line-edge roughness on TFET and FinFET devices and 32-bit CLA circuits'. Together they form a unique fingerprint.

Cite this