Impacts of work function variation and line-edge roughness on TFET and FinFET devices and logic circuits

Chien Ju Chen, Yin Nien Chen, Ming Long Fan, Vita Pi Ho Hu, Pin Su, Ching Te Chuang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

In this paper, we analyze the variability of III-V homojunction tunnel FET (TFET) and FinFET devices and logic circuits operating in near-threshold region. The impacts of work function variation (WFV) and fin line-edge roughness (fin LER) on TFET and FinFET device Ion, Ioff, Cg, two-way NAND delay, switching energy and leakage power are investigated and compared using 3D atomistic TCAD mixed-mode Monte-Carlo simulations. The results indicate that WFV and fin LER have different impacts on ION and IOFF. The delay variability of two-way NAND is aggravated by the Miller capacitance of TFET and FinFET devices.

Original languageEnglish
Title of host publication2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479974382
DOIs
StatePublished - 30 Jan 2014
Event2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014 - Millbrae, United States
Duration: 6 Oct 20149 Oct 2014

Publication series

Name2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014

Conference

Conference2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014
CountryUnited States
CityMillbrae
Period6/10/149/10/14

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