Impacts of wire-LER on nanowire MOSFET devices, subthreshold SRAM and logic circuits

Ming Fu Tsai*, Barney K. Lu, Ming Long Fan, Chia Hao Pao, Yin Nien Chen, Vita Pi Ho Hu, Pin Su, Ching Te Chuang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

We propose a methodology to simulate realistic 2D Line Edge Roughness (LER) pattern for NanoWire (NW) MOSFETs in TCAD platform. This approach predicts the device characteristic and variations including V th, I on and Subthreshold Swing (S.S.) fluctuations more accurately compared with prior literature considering two types of primarily 1D NW geometry variation [1]. Based on the proposed simulation approach, we carry out a comprehensive analysis using 3D atomistic TCAD and mixed-mode Monte Carlo simulations on the impacts of Wire-LER on the variability of NW MOSFET device characteristics, stability of 6T SRAM operating in subthreshold region and logic circuits. The results are extensively compared with previous approaches to illustrate the deficiency of modeling and predictions based on 1D NW geometry variation.

Original languageEnglish
Title of host publication2012 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2012 - Proceedings of Technical Papers
DOIs
StatePublished - 16 Jul 2012
Event2012 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2012 - Hsinchu, Taiwan
Duration: 23 Apr 201225 Apr 2012

Publication series

NameInternational Symposium on VLSI Technology, Systems, and Applications, Proceedings
ISSN (Print)1930-8868

Conference

Conference2012 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2012
CountryTaiwan
CityHsinchu
Period23/04/1225/04/12

Fingerprint Dive into the research topics of 'Impacts of wire-LER on nanowire MOSFET devices, subthreshold SRAM and logic circuits'. Together they form a unique fingerprint.

Cite this