Impacts of NBTI/PBTI on timing control circuits and degradation tolerant design in nanoscale CMOS SRAM

Hao I. Yang*, Shyh Chyi Yang, Wei Hwang, Ching Te Chuang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

27 Scopus citations

Abstract

Negative-bias temperature instability (NBTI) and positive-bias temperature instability (PBTI) weaken PFET and NFET over the lifetime of usage, leading to performance and reliability degradation of nanoscale CMOS SRAM. In addition, most of the state-of-the-art SRAM designs employ replica timing control circuit to mitigate the effects of leakage and process variation, optimize the performance, and reduce power consumption. NBTI and PBTI also degrade the timing control circuits and may render them ineffective. In this paper, we provide comprehensive analyses on the impacts of NBTI and PBTI on a two-port 8T SRAM design, including the stability and Write margin of the cell, Read/Write access paths, and replica timing control circuits. We show, for the first time, that because the Read/Write replica timing control circuits are activated in every Read/Write cycle, they exhibit distinctively different degradation behavior from the normal array access paths, resulting in degradation of timing control and performance. We also discuss degradation tolerant design techniques to mitigate the performance and reliability degradation induced by NBTI/PBTI.

Original languageEnglish
Article number5680621
Pages (from-to)1239-1251
Number of pages13
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume58
Issue number6
DOIs
StatePublished - 10 Jan 2011

Keywords

  • Negative bias temperature instability (NBTI)
  • positive bias temperature instability (PBTI)
  • reliability
  • replica timing control circuit
  • SRAM

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