Impacts of NBTI/PBTI and contact resistance on power-gated SRAM with high-κ Metal-gate devices

Hao I. Yang*, Wei Hwang, Ching Te Chuang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

36 Scopus citations

Abstract

The threshold voltage (VTH) drifts induced by negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) weaken PFETs and high-k metal-gate NFETs, respectively. These long-term V TH drifts degrade SRAM cell stability, margin, and performance, and may lead to functional failure over the life of usage. Meanwhile, the contact resistance of CMOS device increases sharply with technology scaling, especially in SRAM cells with minimum size and/or sub-ground rule devices. The contact resistance, together with NBTI/PBTI, cumulatively worsens the SRAM stability, and leads to severe SRAM performance degradation. Furthermore, most state-of-the-art SRAMs are designed with power-gating structures to reduce leakage currents in Standby or Sleep mode. The power switches could suffer NBTI or PBTI degradation and have large contact resistances. This paper presents a comprehensive analysis on the impacts of NBTI and PBTI on power-gated SRAM arrays with high-k metal-gate devices and the combined effects with the contact resistance on SRAM cell stability, margin, and performance. NBTI/PBTI tolerant sense amplifier structures are also discussed.

Original languageEnglish
Article number5464390
Pages (from-to)1192-1204
Number of pages13
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume19
Issue number7
DOIs
StatePublished - 1 Jul 2011

Keywords

  • Contact resistance
  • negative bias temperature instability (NBTI)
  • positive bias temperature instability (PBTI)
  • power-gated SRAM
  • reliability.

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