Impacts of multiple-gated configuration on the characteristics of poly-si nanowire SONOS devices

Hsing Hui Hsu*, Horng-Chih Lin, Cheng Wei Luo, Chun Jung Su, Tiao Yuan Huang

*Corresponding author for this work

Research output: Contribution to journalArticle

10 Scopus citations

Abstract

In this paper, we have proposed a simple and novel way to fabricate poly-Si nanowire (NW)-silicon-oxide-nitride-oxide-silicon (SONOS) devices with various gate configurations. Three types of devices having various gate configurations, such as side gated, Ω-shaped gated ΩG, and gate-all-around (GAA), were successfully fabricated and characterized. The experimental results show that, owing to the superior gate controllability over NW channels, much improved transfer characteristics are achieved with the GAA devices, as compared with the other types of devices. Moreover, GAA devices also exhibit the best memory characteristics among all splits, including the fastest programming/erasing efficiency, largest memory window, and best endurance/retention characteristics, highlighting the potential of such scheme for future SONOS applications.

Original languageEnglish
Article number5699915
Pages (from-to)641-649
Number of pages9
JournalIEEE Transactions on Electron Devices
Volume58
Issue number3
DOIs
StatePublished - 1 Mar 2011

Keywords

  • Field-effect transistor (FET)
  • multiple gate (MG)
  • nanowire (NW)
  • poly-Si
  • silicon-oxide-nitride-oxide-silicon (SONOS)

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