Impacts of multiple-gate configuration on characteristics of poly-Si nanowire SONOS devices

Hsing Hui Hsu*, Shuan Yun Huang, Chun Jung Su, Horng-Chih Lin, Tiao Yuan Huang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The adoption of the NW structure as the channel has been shown to be beneficial for enhancing the SONOS device performance in terms of lower programming/erasing (P/E) operation voltage, higher P/E speed, and better reliability [1]. However, most of the conventional NW formation processes, either top-down or bottom-up approaches, are cumbersome and costly. To alleviate this problem, we have recently developed several simple and low-cost methods to fabricate NW devices with multiple-gate (MG) configurations [2]-[4]. In this study, we have modified a previous scheme [4] to fabricate and characterize NW SONOS devices with various gate configurations, including side-gate (SG), omega-gate (ωG) and gate-all-around (GAA) structures.

Original languageEnglish
Title of host publicationProceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010
Pages42-43
Number of pages2
DOIs
StatePublished - 20 Oct 2010
Event2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010 - Hsin Chu, Taiwan
Duration: 26 Apr 201028 Apr 2010

Publication series

NameProceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010

Conference

Conference2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010
CountryTaiwan
CityHsin Chu
Period26/04/1028/04/10

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