Impacts of high-κ offset spacer on 65-nm node SOI devices

Ming Wen Ma*, Tien-Sheng Chao, Kuo Hsing Kao, Jyun Siang Huang, Tan Fu Lei

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this paper, the 65 -nm node SOI devices with high-K offset spacer dielectric was investigated by a two-dimensional device simulation. Calculated results show that the high-K offset spacer dielectric can effectively increase the on-state driving current Ion and reduce the off-state leakage current I off due to the high vertical fringing electric field effect arising from the side capacitor comprising of gate/offset spacer/drain extension structure. This fringing field and, in turn, the Ion/Ioff current ratio and subthreshold swing can be strongly enhanced by increasing the dielectric constant of the offset spacer.

Original languageEnglish
Title of host publication2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings
Pages697-700
Number of pages4
StatePublished - 12 Dec 2006
Event2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings - Boston, MA, United States
Duration: 7 May 200611 May 2006

Publication series

Name2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings
Volume1

Conference

Conference2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings
CountryUnited States
CityBoston, MA
Period7/05/0611/05/06

Keywords

  • Fringing electric field
  • High-κ
  • Offset spacer dielectric
  • Silicon-on-insulator (SOI)

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