TY - GEN
T1 - Impacts of contact resistance and NBTI/PBTI on SRAM with high-κ metal-gate devices
AU - Yang, Hao I.
AU - Chuang, Ching Te
AU - Hwang, Wei
PY - 2009/12/25
Y1 - 2009/12/25
N2 - The contact resistance of CMOS device increases sharply with technology scaling, especially in SRAM cells with minimum size and/or sub-groundrule devices. Meanwhile, VT drifts caused by Negative-Bias Temperature Instability (NBTI) and Positive-Bias Temperature Instability (PBTI) degrade stability, margin, and performance of nanoscale SRAM with high-κ metal-gate devices over the lifetime of usage. In this work, we comprehensively analyze the impacts of contact resistance and the combined effects with NBTI and PBTI on SRAM cell stability, margin, and performance. The effect of contact resistance on power-gated SARM is also investigated.
AB - The contact resistance of CMOS device increases sharply with technology scaling, especially in SRAM cells with minimum size and/or sub-groundrule devices. Meanwhile, VT drifts caused by Negative-Bias Temperature Instability (NBTI) and Positive-Bias Temperature Instability (PBTI) degrade stability, margin, and performance of nanoscale SRAM with high-κ metal-gate devices over the lifetime of usage. In this work, we comprehensively analyze the impacts of contact resistance and the combined effects with NBTI and PBTI on SRAM cell stability, margin, and performance. The effect of contact resistance on power-gated SARM is also investigated.
UR - http://www.scopus.com/inward/record.url?scp=72349093772&partnerID=8YFLogxK
U2 - 10.1109/MTDT.2009.25
DO - 10.1109/MTDT.2009.25
M3 - Conference contribution
AN - SCOPUS:72349093772
SN - 9780769537979
T3 - Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009
SP - 27
EP - 30
BT - Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009
Y2 - 31 August 2009 through 2 September 2009
ER -