Impacts of contact resistance and NBTI/PBTI on SRAM with high-κ metal-gate devices

Hao I. Yang; Ching Te Chuang; Wei Hwang

doi:10.1109/MTDT.2009.25

Impacts of contact resistance and NBTI/PBTI on SRAM with high-κ metal-gate devices

Hao I. Yang^*, Ching Te Chuang, Wei Hwang

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

The contact resistance of CMOS device increases sharply with technology scaling, especially in SRAM cells with minimum size and/or sub-groundrule devices. Meanwhile, V_T drifts caused by Negative-Bias Temperature Instability (NBTI) and Positive-Bias Temperature Instability (PBTI) degrade stability, margin, and performance of nanoscale SRAM with high-κ metal-gate devices over the lifetime of usage. In this work, we comprehensively analyze the impacts of contact resistance and the combined effects with NBTI and PBTI on SRAM cell stability, margin, and performance. The effect of contact resistance on power-gated SARM is also investigated.

Original language	English
Title of host publication	Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009
Pages	27-30
Number of pages	4
DOIs	https://doi.org/10.1109/MTDT.2009.25
State	Published - 25 Dec 2009
Event	2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009 - Hsinchu, Taiwan Duration: 31 Aug 2009 → 2 Sep 2009

Publication series

Name	Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009

Conference

Conference	2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009
Country	Taiwan
City	Hsinchu
Period	31/08/09 → 2/09/09

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10.1109/MTDT.2009.25

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Yang, H. I., Chuang, C. T., & Hwang, W. (2009). Impacts of contact resistance and NBTI/PBTI on SRAM with high-κ metal-gate devices. In Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009 (pp. 27-30). [5279848] (Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009). https://doi.org/10.1109/MTDT.2009.25

@inproceedings{54791247ac434eff9e6afe37686f0ba1,

title = "Impacts of contact resistance and NBTI/PBTI on SRAM with high-κ metal-gate devices",

abstract = "The contact resistance of CMOS device increases sharply with technology scaling, especially in SRAM cells with minimum size and/or sub-groundrule devices. Meanwhile, VT drifts caused by Negative-Bias Temperature Instability (NBTI) and Positive-Bias Temperature Instability (PBTI) degrade stability, margin, and performance of nanoscale SRAM with high-κ metal-gate devices over the lifetime of usage. In this work, we comprehensively analyze the impacts of contact resistance and the combined effects with NBTI and PBTI on SRAM cell stability, margin, and performance. The effect of contact resistance on power-gated SARM is also investigated.",

author = "Yang, {Hao I.} and Chuang, {Ching Te} and Wei Hwang",

year = "2009",

month = dec,

day = "25",

doi = "10.1109/MTDT.2009.25",

language = "English",

isbn = "9780769537979",

series = "Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009",

pages = "27--30",

booktitle = "Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009",

note = "null ; Conference date: 31-08-2009 Through 02-09-2009",

}

Yang, HI, Chuang, CT & Hwang, W 2009, Impacts of contact resistance and NBTI/PBTI on SRAM with high-κ metal-gate devices. in Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009., 5279848, Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009, pp. 27-30, 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009, Hsinchu, Taiwan, 31/08/09. https://doi.org/10.1109/MTDT.2009.25

Impacts of contact resistance and NBTI/PBTI on SRAM with high-κ metal-gate devices. / Yang, Hao I.; Chuang, Ching Te; Hwang, Wei.

Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009. 2009. p. 27-30 5279848 (Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Chuang, Ching Te

AU - Hwang, Wei

PY - 2009/12/25

Y1 - 2009/12/25

N2 - The contact resistance of CMOS device increases sharply with technology scaling, especially in SRAM cells with minimum size and/or sub-groundrule devices. Meanwhile, VT drifts caused by Negative-Bias Temperature Instability (NBTI) and Positive-Bias Temperature Instability (PBTI) degrade stability, margin, and performance of nanoscale SRAM with high-κ metal-gate devices over the lifetime of usage. In this work, we comprehensively analyze the impacts of contact resistance and the combined effects with NBTI and PBTI on SRAM cell stability, margin, and performance. The effect of contact resistance on power-gated SARM is also investigated.

AB - The contact resistance of CMOS device increases sharply with technology scaling, especially in SRAM cells with minimum size and/or sub-groundrule devices. Meanwhile, VT drifts caused by Negative-Bias Temperature Instability (NBTI) and Positive-Bias Temperature Instability (PBTI) degrade stability, margin, and performance of nanoscale SRAM with high-κ metal-gate devices over the lifetime of usage. In this work, we comprehensively analyze the impacts of contact resistance and the combined effects with NBTI and PBTI on SRAM cell stability, margin, and performance. The effect of contact resistance on power-gated SARM is also investigated.

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Yang HI, Chuang CT, Hwang W. Impacts of contact resistance and NBTI/PBTI on SRAM with high-κ metal-gate devices. In Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009. 2009. p. 27-30. 5279848. (Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009). https://doi.org/10.1109/MTDT.2009.25

Impacts of contact resistance and NBTI/PBTI on SRAM with high-κ metal-gate devices

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