Impacts of contact resistance and NBTI/PBTI on SRAM with high-κ metal-gate devices

Hao I. Yang*, Ching Te Chuang, Wei Hwang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

The contact resistance of CMOS device increases sharply with technology scaling, especially in SRAM cells with minimum size and/or sub-groundrule devices. Meanwhile, VT drifts caused by Negative-Bias Temperature Instability (NBTI) and Positive-Bias Temperature Instability (PBTI) degrade stability, margin, and performance of nanoscale SRAM with high-κ metal-gate devices over the lifetime of usage. In this work, we comprehensively analyze the impacts of contact resistance and the combined effects with NBTI and PBTI on SRAM cell stability, margin, and performance. The effect of contact resistance on power-gated SARM is also investigated.

Original languageEnglish
Title of host publicationProceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009
Pages27-30
Number of pages4
DOIs
StatePublished - 25 Dec 2009
Event2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009 - Hsinchu, Taiwan
Duration: 31 Aug 20092 Sep 2009

Publication series

NameProceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009

Conference

Conference2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009
CountryTaiwan
CityHsinchu
Period31/08/092/09/09

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    Yang, H. I., Chuang, C. T., & Hwang, W. (2009). Impacts of contact resistance and NBTI/PBTI on SRAM with high-κ metal-gate devices. In Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009 (pp. 27-30). [5279848] (Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009). https://doi.org/10.1109/MTDT.2009.25