Impact of systematic spatial intra-chip gate length variability on performance of high-speed digital circuits

Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chen-Ming Hu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

57 Scopus citations

Abstract

Using data collected from an actual state-of-the-art fabrication facility, we conducted a comprehensive characterization of an advanced 0.18 μmCMOS process. The measured data revealed significant systematic, rather than random, spatial intra-chip variability of MOS gate length, leading to large circuit path delay variation. The critical path value of a combinational logic block varies by as much as 17%, and the global skew is increased by 8%. Thus, a significant timing error (-25%) and performance loss takes place if variability is not properly addressed. We derive a model, which allows estimating performance degradation for the given circuit and process parameters. Analysis shows that the spatial, rather than proximitydependent, systematic Lgate variability is the main cause of large circuit speed degradation. The degradation is worse for the circuits with a larger number of critical paths and shorter average logic depth. We propose a location-dependent timing analysis methodology that allows to mitigate the detrimental effects of Lgate variability, and developed a tool linking the layout-dependent spatial information to circuit analysis. We discuss the details of the practical implementation of the methodology, and provide the guidelines for managing the design complexity.

Original languageEnglish
Title of host publicationIEEE/ACM International Conference on Computer Aided Design
Subtitle of host publicationA Conference for the EE CAD Professional, ICCAD 2000
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages62-67
Number of pages6
ISBN (Electronic)0780364457
DOIs
StatePublished - 1 Jan 2000
EventIEEE/ACM International Conference on Computer Aided Design, ICCAD 2000 - San Jose, United States
Duration: 5 Nov 20009 Nov 2000

Publication series

NameIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
Volume2000-January
ISSN (Print)1092-3152

Conference

ConferenceIEEE/ACM International Conference on Computer Aided Design, ICCAD 2000
CountryUnited States
CitySan Jose
Period5/11/009/11/00

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    Orshansky, M., Milor, L., Chen, P., Keutzer, K., & Hu, C-M. (2000). Impact of systematic spatial intra-chip gate length variability on performance of high-speed digital circuits. In IEEE/ACM International Conference on Computer Aided Design: A Conference for the EE CAD Professional, ICCAD 2000 (pp. 62-67). [896452] (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD; Vol. 2000-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCAD.2000.896452