Impact of strain layer on gate leakage and interface-state for nMOSFETs fabricated by stress-memorization technique

Chia Chun Liao*, Min Chen Lin, Tsung Yu Chiang, Tien-Sheng Chao

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

This paper investigates the impact of stress memorization on the interface-state for n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETS). We found that both the initial component of the deposited capping layer and the H released during annealing affected interface-state passivation. The annealed stress is responsible for degraded gate-leakage characteristics. Based on electrical performance and gate leakage, an initial compressive layer of SiN performs better than an initial tensile layer for the stress-memorization technique process.

Original languageEnglish
JournalElectrochemical and Solid-State Letters
Volume14
Issue number1
DOIs
StatePublished - 24 Jan 2011

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