Impact of shielding line on CDM ESD robustness of core circuits in a 65-nm CMOS process

Ming-Dou Ker*, Chun Yu Lin, Chang Tang-Long Chang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

The charged-device-model (CDM) ESD robustness of core circuit with/without the shielding line was studied in a 65-nm CMOS process. Verified in silicon chip, the CDM ESD robustness of core circuit with the shielding line was degraded. The damage mechanism and failure location of the test circuits were investigated in this work.

Original languageEnglish
Title of host publication2011 International Reliability Physics Symposium, IRPS 2011
DOIs
StatePublished - 23 Jun 2011
Event49th International Reliability Physics Symposium, IRPS 2011 - Monterey, CA, United States
Duration: 10 Apr 201114 Apr 2011

Publication series

NameIEEE International Reliability Physics Symposium Proceedings
ISSN (Print)1541-7026

Conference

Conference49th International Reliability Physics Symposium, IRPS 2011
CountryUnited States
CityMonterey, CA
Period10/04/1114/04/11

Keywords

  • Charged-device model (CDM)
  • ESD
  • shielding line

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    Ker, M-D., Lin, C. Y., & Tang-Long Chang, C. (2011). Impact of shielding line on CDM ESD robustness of core circuits in a 65-nm CMOS process. In 2011 International Reliability Physics Symposium, IRPS 2011 [5784565] (IEEE International Reliability Physics Symposium Proceedings). https://doi.org/10.1109/IRPS.2011.5784565