Impact of process variations on leakage power in CMOS circuits in nano era

A. N. Chandorkar; Ch Ragunandan; Pradyumna Agashe; Dinesh Sharma; Hiroshi Iwai

doi:10.1109/ICSICT.2006.306105

Impact of process variations on leakage power in CMOS circuits in nano era

A. N. Chandorkar^*, Ch Ragunandan, Pradyumna Agashe, Dinesh Sharma, Hiroshi Iwai

^*Corresponding author for this work

International College of Semiconductor Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

In sub 90 nm CMOS technology the process variations seriously affect the performance specification for leakage power and delay. In this paper, we have analyzed the techniques to improve the design quality for power and performance sensitivity to process variations. At gate level forced stacking not only reduces leakage but also improves the robustness of the gate to process variations. Logic style level the variation of leakage current with the Vth variation for various logic styles is studied.

Original language	English
Title of host publication	ICSICT-2006
Subtitle of host publication	2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings
Publisher	IEEE Computer Society
Pages	1248-1251
Number of pages	4
ISBN (Print)	1424401615, 9781424401611
DOIs	https://doi.org/10.1109/ICSICT.2006.306105
State	Published - 2006
Event	ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology - Shanghai, China Duration: 23 Oct 2006 → 26 Oct 2006

Publication series

Name	ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings

Conference

Conference	ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology
Country	China
City	Shanghai
Period	23/10/06 → 26/10/06

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Chandorkar, A. N., Ragunandan, C., Agashe, P., Sharma, D., & Iwai, H. (2006). Impact of process variations on leakage power in CMOS circuits in nano era. In ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings (pp. 1248-1251). [4098374] (ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings). IEEE Computer Society. https://doi.org/10.1109/ICSICT.2006.306105

Chandorkar, A. N. ; Ragunandan, Ch ; Agashe, Pradyumna ; Sharma, Dinesh ; Iwai, Hiroshi. / Impact of process variations on leakage power in CMOS circuits in nano era. ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings. IEEE Computer Society, 2006. pp. 1248-1251 (ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings).

@inproceedings{5c6a89292a1941ffbed7d4338ad004a8,

title = "Impact of process variations on leakage power in CMOS circuits in nano era",

abstract = "In sub 90 nm CMOS technology the process variations seriously affect the performance specification for leakage power and delay. In this paper, we have analyzed the techniques to improve the design quality for power and performance sensitivity to process variations. At gate level forced stacking not only reduces leakage but also improves the robustness of the gate to process variations. Logic style level the variation of leakage current with the Vth variation for various logic styles is studied.",

author = "Chandorkar, {A. N.} and Ch Ragunandan and Pradyumna Agashe and Dinesh Sharma and Hiroshi Iwai",

year = "2006",

doi = "10.1109/ICSICT.2006.306105",

language = "English",

isbn = "1424401615",

series = "ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings",

publisher = "IEEE Computer Society",

pages = "1248--1251",

booktitle = "ICSICT-2006",

address = "United States",

note = "null ; Conference date: 23-10-2006 Through 26-10-2006",

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Chandorkar, AN, Ragunandan, C, Agashe, P, Sharma, D & Iwai, H 2006, Impact of process variations on leakage power in CMOS circuits in nano era. in ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings., 4098374, ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings, IEEE Computer Society, pp. 1248-1251, ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Shanghai, China, 23/10/06. https://doi.org/10.1109/ICSICT.2006.306105

Impact of process variations on leakage power in CMOS circuits in nano era. / Chandorkar, A. N.; Ragunandan, Ch; Agashe, Pradyumna; Sharma, Dinesh; Iwai, Hiroshi.

ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings. IEEE Computer Society, 2006. p. 1248-1251 4098374 (ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Impact of process variations on leakage power in CMOS circuits in nano era

AU - Chandorkar, A. N.

AU - Ragunandan, Ch

AU - Agashe, Pradyumna

AU - Sharma, Dinesh

AU - Iwai, Hiroshi

PY - 2006

Y1 - 2006

N2 - In sub 90 nm CMOS technology the process variations seriously affect the performance specification for leakage power and delay. In this paper, we have analyzed the techniques to improve the design quality for power and performance sensitivity to process variations. At gate level forced stacking not only reduces leakage but also improves the robustness of the gate to process variations. Logic style level the variation of leakage current with the Vth variation for various logic styles is studied.

AB - In sub 90 nm CMOS technology the process variations seriously affect the performance specification for leakage power and delay. In this paper, we have analyzed the techniques to improve the design quality for power and performance sensitivity to process variations. At gate level forced stacking not only reduces leakage but also improves the robustness of the gate to process variations. Logic style level the variation of leakage current with the Vth variation for various logic styles is studied.

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U2 - 10.1109/ICSICT.2006.306105

DO - 10.1109/ICSICT.2006.306105

M3 - Conference contribution

AN - SCOPUS:34547257247

SN - 1424401615

SN - 9781424401611

T3 - ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings

SP - 1248

EP - 1251

BT - ICSICT-2006

PB - IEEE Computer Society

Y2 - 23 October 2006 through 26 October 2006

ER -

Chandorkar AN, Ragunandan C, Agashe P, Sharma D, Iwai H. Impact of process variations on leakage power in CMOS circuits in nano era. In ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings. IEEE Computer Society. 2006. p. 1248-1251. 4098374. (ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings). https://doi.org/10.1109/ICSICT.2006.306105

Impact of process variations on leakage power in CMOS circuits in nano era

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