Impact of process variations on leakage power in CMOS circuits in nano era

A. N. Chandorkar*, Ch Ragunandan, Pradyumna Agashe, Dinesh Sharma, Hiroshi Iwai

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

In sub 90 nm CMOS technology the process variations seriously affect the performance specification for leakage power and delay. In this paper, we have analyzed the techniques to improve the design quality for power and performance sensitivity to process variations. At gate level forced stacking not only reduces leakage but also improves the robustness of the gate to process variations. Logic style level the variation of leakage current with the Vth variation for various logic styles is studied.

Original languageEnglish
Title of host publicationICSICT-2006
Subtitle of host publication2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings
PublisherIEEE Computer Society
Pages1248-1251
Number of pages4
ISBN (Print)1424401615, 9781424401611
DOIs
StatePublished - 2006
EventICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology - Shanghai, China
Duration: 23 Oct 200626 Oct 2006

Publication series

NameICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings

Conference

ConferenceICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology
CountryChina
CityShanghai
Period23/10/0626/10/06

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