Impact of polysilicon depletion in thin oxide MOS technology

Klaus F. Schuegraf, C. C. King, Chen-Ming Hu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

35 Scopus citations

Abstract

Accurate characterization of thin oxide conduction current, breakdown, and MOSFET current require an accounting for the voltage drop due to the depletion of the polysilicon gate. The reduction of oxide thickness and polysilicon doping ascerbate this effect. Scaled n+/p+ dual gate CMOS technology incorporates both these trends, due to process integration constraints which limit the concentration of active dopants in polysilicon. This paper investigates effects of polysilicon depletion on the thin oxide MOS system.

Original languageEnglish
Title of host publication1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages86-90
Number of pages5
ISBN (Electronic)0780309782
DOIs
StatePublished - 1 Jan 1993
Event1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Taipei, Taiwan
Duration: 12 May 199314 May 1993

Publication series

NameInternational Symposium on VLSI Technology, Systems, and Applications, Proceedings
ISSN (Print)1930-8868

Conference

Conference1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993
CountryTaiwan
CityTaipei
Period12/05/9314/05/93

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