Impact of layout pickups to ESD robustness of MOS transistors in sub 100-nm CMOS process

Ming-Dou Ker*, Yong Ru Wen, Wen Yi Chen, Chun Yu Lin

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Scopus citations

Abstract

Electrostatic discharge (ESD) is an inevitable event in CMOS integrated circuits. Layout structure is one of the im portant factors that affect ESD robustness of MOS transistors. In this work, the impact of inserting additional layout pickups to ESD robustness of both multi-finger NMOS and PMOS transistors has been studied in a 90-nm CMOS process. Measurement results have shown that multi-finger MOS transistors without additional pickup inserted into their source regions can sustain a higher ESD protection level at the same effective device dimension.

Original languageEnglish
Title of host publication2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program
Pages100-103
Number of pages4
DOIs
StatePublished - 1 Dec 2010
Event2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Kaohsiung, Taiwan
Duration: 18 Nov 201019 Nov 2010

Publication series

Name2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program

Conference

Conference2010 International Symposium on Next-Generation Electronics, ISNE 2010
CountryTaiwan
CityKaohsiung
Period18/11/1019/11/10

Keywords

  • Electrostatic discharge (ESD)
  • Pickup

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    Ker, M-D., Wen, Y. R., Chen, W. Y., & Lin, C. Y. (2010). Impact of layout pickups to ESD robustness of MOS transistors in sub 100-nm CMOS process. In 2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program (pp. 100-103). [5669188] (2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program). https://doi.org/10.1109/ISNE.2010.5669188