Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection

Seian Feng Liao, Kai Neng Tang, Ming-Dou Ker, Jia Rong Yeh, Hwa Chyi Chiou, Yeh Jen Huang, Chun Chien Tsai, Yeh Ning Jou, Geeng Lih Lin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Electrostatic discharge (ESD) protection and latchup prevention are two important reliability issues to the CMOS integrated circuits, especially in high-voltage (HV) applications. In this work, the stacked low-voltage (LV) PMOS devices have been successfully verified in a 0.5-μm HV process to provide high ESD level with high holding voltage for HV applications. In addition, the guard-ring layout on the stacked LV PMOS devices was further investigated in silicon chip to get high ESD robustness and latchup-free immunity for HV applications.

Original languageEnglish
Title of host publication2015 European Conference on Circuit Theory and Design, ECCTD 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479998777
DOIs
StatePublished - 16 Oct 2015
EventEuropean Conference on Circuit Theory and Design, ECCTD 2015 - Trondheim, Norway
Duration: 24 Aug 201526 Aug 2015

Publication series

Name2015 European Conference on Circuit Theory and Design, ECCTD 2015

Conference

ConferenceEuropean Conference on Circuit Theory and Design, ECCTD 2015
CountryNorway
CityTrondheim
Period24/08/1526/08/15

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