Impact of gate tunneling leakage on performances of phase locked loop circuit in nanoscale CMOS technology

Jung Sheng Chen*, Ming-Dou Ker

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

The influence of gate tunneling leakage on the circuit performances of phase locked loop (PLL) in nanoscale CMOS technology has been investigated by simulation. The basic PLL with second-order loop filter is used to simulate the impact of gate tunneling leakage on performance degradation of PLL in a standard 90-nm CMOS process. The MOS capacitors with different oxide thicknesses are used to investigate this impact to PLL. The locked time, static phase error, and jitter of second-order PLL are degraded by the gate tunneling leakage of MOS capacitor in loop filter.

Original languageEnglish
Title of host publication2007 IEEE International Reliability Physics Symposium Proceedings, 45th Annual
Pages664-665
Number of pages2
DOIs
StatePublished - 25 Sep 2007
Event45th Annual IEEE International Reliability Physics Symposium 2007, IRPS - Phoenix, AZ, United States
Duration: 15 Apr 200719 Apr 2007

Publication series

NameAnnual Proceedings - Reliability Physics (Symposium)
ISSN (Print)0099-9512

Conference

Conference45th Annual IEEE International Reliability Physics Symposium 2007, IRPS
CountryUnited States
CityPhoenix, AZ
Period15/04/0719/04/07

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