Impact of gate-oxide breakdown on power-gated SRAM

Hao I. Yang*, Ching Te Chuang, Wei Hwang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

This paper presents a detailed analysis on the impacts of various gate-oxide breakdown (BD) paths in column-based header- and footer-gated SRAMs. It is shown that with gate-oxide BD, the RSNM (Read Static Noise Margin) degrades, while the WM (Write Margin) improves in general. The effects of gate-to-source BD of cell transistors are shown to confine to the individual cell, while multiple cells suffering cell transistor drain-to-drain BD in a column could cumulatively affect VVDD (header structure) or VVSS (footer structure), thus influencing other cells in the same column. In particular, we show that the gate-oxide BD of the power-switches have server and even detrimental effects on the margin, stability, and performance of the SRAM array.

Original languageEnglish
Title of host publication2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009
Pages93-96
Number of pages4
DOIs
StatePublished - 1 Dec 2009
Event2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009 - Austin, TX, United States
Duration: 18 May 200920 May 2009

Publication series

Name2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009

Conference

Conference2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009
CountryUnited States
CityAustin, TX
Period18/05/0920/05/09

Keywords

  • Gate-oxide breakdown
  • Power gating technology
  • SRAM

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