Impact of gate leakage on performances of phase-locked loop circuit in nanoscale CMOS technology

Jung Sheng Chen*, Ming-Dou Ker

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

6 Scopus citations

Abstract

In the nanoscale CMOS technology, the thin gate oxide causes large gate-tunneling leakage. In this brief, the influence of gate-tunneling leakage in the MOS capacitor (used in the loop filter) on the circuit performance of the phase-locked loop (PLL) in the nanoscale CMOS technology has been investigated and analyzed. The basic PLL with a second-order loop filter is used to observe the impact of gate-tunneling leakage on the performance degradation of the PLL in a 90-nm CMOS process. The MOS capacitors with different oxide thicknesses are used to investigate their impact on the PLL performance. The locked time, static phase error, and jitter of the second-order PLL are found to be degraded by the gate-tunneling leakage of the MOS capacitor used in the loop filter.

Original languageEnglish
Pages (from-to)1774-1779
Number of pages6
JournalIEEE Transactions on Electron Devices
Volume56
Issue number8
DOIs
StatePublished - 23 Jun 2009

Keywords

  • Gate-tunneling leakage
  • Loop filter
  • MOS capacitor
  • Phase-locked loop (PLL)

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