Impact of CMOS scaling on RF/MMIC designs

Mau-Chung Chang, Daquan Huang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Recent performance advancement in superscaled CMOS technologies has opened new avenues for implementing RF/MMICs on cost-effective mainstream silicon substrate. This talk addresses critical issues involved in designing those high-frequency circuits under technology constraints of decreasing supply voltage and device gain, increasing device mismatch and metal & substrate losses. The talk will also discuss possible circuit level solutions in both topology and signaling, which may mitigate those constraints and deliver demanded performance and functions for future high frequency communication systems.

Original languageEnglish
Title of host publicationRFIT 2007 - IEEE International Workshop on Radio-Frequency Integration Technology
Pages183-187
Number of pages5
DOIs
StatePublished - 1 Dec 2007
EventIEEE International Workshop on Radio-Frequency Integration Technology, RFIT 2007 - Singapore, Singapore
Duration: 9 Dec 200711 Dec 2007

Publication series

NameRFIT 2007 - IEEE International Workshop on Radio-Frequency Integration Technology

Conference

ConferenceIEEE International Workshop on Radio-Frequency Integration Technology, RFIT 2007
CountrySingapore
CitySingapore
Period9/12/0711/12/07

Keywords

  • Circuit topology and signaling
  • CMOS scaling
  • High-Q passives
  • MMIC
  • RFIC

Fingerprint Dive into the research topics of 'Impact of CMOS scaling on RF/MMIC designs'. Together they form a unique fingerprint.

  • Cite this

    Chang, M-C., & Huang, D. (2007). Impact of CMOS scaling on RF/MMIC designs. In RFIT 2007 - IEEE International Workshop on Radio-Frequency Integration Technology (pp. 183-187). [4443946] (RFIT 2007 - IEEE International Workshop on Radio-Frequency Integration Technology). https://doi.org/10.1109/RFIT.2007.4443946