A new DA (distributed arithmetic) method called ladder-based DA is proposed to evaluate the inner products of vectors. The proposed method needs only 13% of transistor count and 30% of ROM area with comparable performance. A 2D IDCT (Inverse Discrete Cosine Transform) chip is designed and implemented on the adder-based DA to verify the correctness and efficiency of the method.
|Number of pages||2|
|State||Published - 1 Jan 1996|
|Event||Proceedings of the 1996 Symposium on VLSI Circuits - Honolulu, HI, USA|
Duration: 13 Jun 1996 → 15 Jun 1996
|Conference||Proceedings of the 1996 Symposium on VLSI Circuits|
|City||Honolulu, HI, USA|
|Period||13/06/96 → 15/06/96|