IDCT processor on the adder-based distributed arithmetic

Chingson Chen; Tian-Sheuan Chang; Chein Wei Jen

IDCT processor on the adder-based distributed arithmetic

Chingson Chen^*, Tian-Sheuan Chang, Chein Wei Jen

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to conference › Paper › peer-review

5 Scopus citations

Abstract

A new DA (distributed arithmetic) method called ladder-based DA is proposed to evaluate the inner products of vectors. The proposed method needs only 13% of transistor count and 30% of ROM area with comparable performance. A 2D IDCT (Inverse Discrete Cosine Transform) chip is designed and implemented on the adder-based DA to verify the correctness and efficiency of the method.

Original language	English
Pages	36-37
Number of pages	2
State	Published - 1 Jan 1996
Event	Proceedings of the 1996 Symposium on VLSI Circuits - Honolulu, HI, USA Duration: 13 Jun 1996 → 15 Jun 1996

Conference

Conference	Proceedings of the 1996 Symposium on VLSI Circuits
City	Honolulu, HI, USA
Period	13/06/96 → 15/06/96

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Cite this

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title = "IDCT processor on the adder-based distributed arithmetic",

abstract = "A new DA (distributed arithmetic) method called ladder-based DA is proposed to evaluate the inner products of vectors. The proposed method needs only 13% of transistor count and 30% of ROM area with comparable performance. A 2D IDCT (Inverse Discrete Cosine Transform) chip is designed and implemented on the adder-based DA to verify the correctness and efficiency of the method.",

author = "Chingson Chen and Tian-Sheuan Chang and Jen, {Chein Wei}",

year = "1996",

month = jan,

day = "1",

language = "English",

pages = "36--37",

note = "null ; Conference date: 13-06-1996 Through 15-06-1996",

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T1 - IDCT processor on the adder-based distributed arithmetic

AU - Chen, Chingson

AU - Chang, Tian-Sheuan

AU - Jen, Chein Wei

PY - 1996/1/1

Y1 - 1996/1/1

N2 - A new DA (distributed arithmetic) method called ladder-based DA is proposed to evaluate the inner products of vectors. The proposed method needs only 13% of transistor count and 30% of ROM area with comparable performance. A 2D IDCT (Inverse Discrete Cosine Transform) chip is designed and implemented on the adder-based DA to verify the correctness and efficiency of the method.

AB - A new DA (distributed arithmetic) method called ladder-based DA is proposed to evaluate the inner products of vectors. The proposed method needs only 13% of transistor count and 30% of ROM area with comparable performance. A 2D IDCT (Inverse Discrete Cosine Transform) chip is designed and implemented on the adder-based DA to verify the correctness and efficiency of the method.

UR - http://www.scopus.com/inward/record.url?scp=0029715112&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0029715112

SP - 36

EP - 37

Y2 - 13 June 1996 through 15 June 1996

ER -