IC design of a high speed RSA processor

Ching Chao Yang*, Chein Wei Jen, Tian-Sheuan Chang

*Corresponding author for this work

Research output: Contribution to conferencePaper

4 Scopus citations

Abstract

In this paper, we proposed a new algorithm based on Montgomery's algorithm[1] to calculate modular multiplication that is the core arithmetic operation in RSA cryptosystem. Since the critical path delay in modular multiplication operation is reduced, the new design yields a very fast implementation. We have implemented a 512-bit single chip RSA processor based on our modified algorithm with Compass 0.6μm SPDM cell library. By our modified modular exponentiation algorithm, it takes about 1.5n2 clock cycles to finish one n-bit RSA modular exponentiation operation in our architecture. The simulation results show that we can operate up to 125Mhz, therefore the baud rate of our 512-bit RSA processor is about 164k bits/sec.

Original languageEnglish
Pages33-36
Number of pages4
DOIs
StatePublished - 1 Dec 1996
EventProceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems - Seoul, South Korea
Duration: 18 Nov 199621 Nov 1996

Conference

ConferenceProceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems
CitySeoul, South Korea
Period18/11/9621/11/96

Fingerprint Dive into the research topics of 'IC design of a high speed RSA processor'. Together they form a unique fingerprint.

  • Cite this

    Yang, C. C., Jen, C. W., & Chang, T-S. (1996). IC design of a high speed RSA processor. 33-36. Paper presented at Proceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems, Seoul, South Korea, . https://doi.org/10.1109/APCAS.1996.569212