Goals of this research are to reduce 1. Instruction address bus traffic, 2. Bus power, and 3. Latency, in instructio fetches in a computer system. We propose to move dynamic branch handler from the CPU side to the instruction memory side, and let it be able to autonomously access instructions for CPU. CPU needs only to manage the branch handler. Key to success is that the traffic between CPU and dynamic branch handler, with only minor but innovative design changes, can be far less than that between CPU and instruction memory. The branch handler should hence be capable of PC+4, identifying branches, and target address calculation. We further suggest that even a return stack can easily be incorporated. Simulation using MiBench shows that our theory yields promising results: about 99.98% instruction address traffic and 91.87% related bus bit toggles are reduced.