Hybrid testbench acceleration for reducing communication overhead

Chin Lung Chuang, Chien-Nan Liu*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

2 Scopus citations


Hybrid embedded testbench acceleration (HETA), a new approach to reduce communication overhead in hardware accelerators, speeds up simulation of chip prototypes by avoiding the communication between hardware and software. Experimental results on an industry design show that the proposed HETA approach is about 10 times faster than a commercial hardware accelerator and with only 0.57 hardware overhead.

Original languageEnglish
Article number5739840
Pages (from-to)40-50
Number of pages11
JournalIEEE Design and Test of Computers
Issue number2
StatePublished - 1 Mar 2011


  • design and test
  • functional verification
  • hardware-accelerated simulation
  • HETA
  • testbench acceleration

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