Hybrid buck-linear (HBL) technique for enhanced dip voltage and transient response in load-preparation buck (LPB) converter

Chun Jen Shih*, Kuan Yu Chu, Yu Huei Lee, Ke-Horng Chen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations

Abstract

A hybrid buck-linear (HBL) technique in a load-preparation buck (LPB) converter for system-on-a-chip (Soc) is proposed in this paper. In case of the sudden load variation in Soc, the proposed converter with hybrid operation can effectively enhance the transient response with smaller dip voltage and faster transient recovery time. In addition, the high power conversion efficiency can be derived since an auxiliary power switch assures that hybrid operation is only activated in load transient period. Experimental results demonstrate that the improvements of transient dip voltage and recovery time are 53 % and 63 %, respectively, as well as 8 % in efficiency. The chip was fabricated by 0.25 μm CMOS process with a peak efficiency of 95 % for Soc applications.

Original languageEnglish
Title of host publicationESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference
Pages431-434
Number of pages4
DOIs
StatePublished - 12 Dec 2011
Event37th European Solid-State Circuits Conference, ESSCIRC 2011 - Helsinki, Finland
Duration: 12 Sep 201116 Sep 2011

Publication series

NameEuropean Solid-State Circuits Conference
ISSN (Print)1930-8833

Conference

Conference37th European Solid-State Circuits Conference, ESSCIRC 2011
CountryFinland
CityHelsinki
Period12/09/1116/09/11

Fingerprint Dive into the research topics of 'Hybrid buck-linear (HBL) technique for enhanced dip voltage and transient response in load-preparation buck (LPB) converter'. Together they form a unique fingerprint.

Cite this