How to safely apply the LVTSCR for CMOS whole-chip ESD protection without being accidentally triggered on

Ming-Dou Ker*, Hun Hsien Chang

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

32 Scopus citations

Abstract

In this paper, the lateral SCR devices used in CMOS on-chip ESD protection circuits are reviewed. Such SCR devices had been found to be accidentally triggered on by noise pulses when the IC's are in the normal operating condition. A cascode design is therefore proposed to safely apply the LVTSCR devices for whole-chip ESD protection in CMOS IC's without causing unexpected operation errors or latchup danger. Such cascoded LVTSCR's with a holding voltage greater than VDD of an IC can provide CMOS IC's with effective component-level ESD protection but without being accidentally triggered on by system-level overshooting or undershooting noise pulses.

Original languageEnglish
Pages (from-to)72-85
Number of pages14
JournalElectrical Overstress/Electrostatic Discharge Symposium Proceedings
DOIs
StatePublished - 1 Dec 1998
EventProceedings of the 1998 20th Annual International EOS/ESD Symposium - Reno, NV, USA
Duration: 6 Oct 19988 Oct 1998

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