Hot Electrons as the Dominant Source of Degradation for Sub-5nm HZO FeFETs

Ava J. Tan, Milan Pesic, Luca Larcher, Yu Hung Liao, Li Chen Wang, Jong Ho Bae, Chenming Hu, Sayeef Salahuddin

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

In this work, we demonstrate FDSOI ferroelectric FETs (FeFETs) incorporating 4.5 nm hafnium zirconium oxide, which show a 0.5V memory window at +/-3.3V and a program/erase speed of 1 u s. In typical FeFETs where \geq 9 nm thick ferroelectric (FE) gate oxides have been used, bulk charge trapping has been identified as the main mechanism for endurance degradation and shrinkage of the memory window (MW). By contrast, we find that the role of bulk trapping in our devices with a much thinner FE layer is minimal. Through a combination of cryogenic temperature-dependent electrical measurements and simulations using the Ginestra ™ modeling platform, we identify and prove that hot electron-induced hole damage during the application of negative gate biases is the primary source of endurance degradation and MW closure in FeFETs with scaled oxide layers.

Original languageEnglish
Title of host publication2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728164601
DOIs
StatePublished - Jun 2020
Event2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020 - Honolulu, United States
Duration: 16 Jun 202019 Jun 2020

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
Volume2020-June
ISSN (Print)0743-1562

Conference

Conference2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020
CountryUnited States
CityHonolulu
Period16/06/2019/06/20

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