Hot-carrier reliability of P-MOSFET with ultra-thin silicon nitride gate dielectric

I. Polishchuk*, Y. C. Yeo, Q. Lu, T. J. King, Chen-Ming Hu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

The degradation of 100 nm effective channel length p-MOS transistors with 14 Å equivalent oxide thickness JVD Si3N4 gate dielectric under hot-carrier stress is studied. Interface-state generation is identified as the dominant degradation mechanism. Hot-carrier-induced gate leakage may become a new reliability concern. Hot-carrier reliability of 14 Å Si3N4 transistors is compared to reliability of 16 Å SiO2 transistors.

Original languageEnglish
Title of host publication2001 IEEE International Reliability Physics Symposium Proceedings - 39th Annual
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages425-430
Number of pages6
ISBN (Electronic)0780365879
DOIs
StatePublished - 1 Jan 2001
Event39th Annual IEEE International Reliability Physics Symposium, IRPS 2001 - Orlando, United States
Duration: 30 Apr 20013 May 2001

Publication series

NameIEEE International Reliability Physics Symposium Proceedings
Volume2001-January
ISSN (Print)1541-7026

Conference

Conference39th Annual IEEE International Reliability Physics Symposium, IRPS 2001
CountryUnited States
CityOrlando
Period30/04/013/05/01

Keywords

  • CMOS process
  • Degradation
  • Dielectric materials
  • Fabrication
  • High K dielectric materials
  • High-K gate dielectrics
  • Hot carriers
  • MOSFET circuits
  • Silicon
  • Stress

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