DC lifetime, in conjunction with speed and time factors, can be used to predict digital circuit hot-carrier lifetime. Analog circuit reliability prediction, on the other hand, has to take analog design variables such as channel length, biasing conditions, and circuit topography into consideration. We propose a new methodology for predicting analog circuit reliability. Instead of the traditional lifetime plots, we present a set of analog hot-carrier design curves that span the analog design space. The design curves will become increasingly important for high speed analog applications and for ULSI chips that integrate a wide variety of analog and digital functions. The design curves can be used to quickly estimate the hot-carrier sensitivity of a particular analog sub-block and to adjust the design variables for better hot-carrier immunity.