Hot-Carrier-Reliability Design Guidelines for CMOS Logic Circuits

Khandker N. Quader, Eric R. Minami, W. J. Wei-Jen, H. Huang, Ping K. Ko, Chen-Ming Hu

Research output: Contribution to journalArticle

22 Scopus citations

Abstract

Long-term ring-oscillator hot-carrier degradation data and simulation results are compared to demonstrate that a circuit reliability simulator BERT can predict CMOS digital circuit speed degradation from transistor dc stress data. We present generalized hot-carrier-reliability design rules that translate device-level degradation rate to CMOS circuit lifetime. The design rules, which consist of lifetime and speed degradation factors, can roughly predict CMOS circuit degradation during the initial design, and can help reliability engineers to quickly estimate the overall product hot-carrier reliability. The NMOSFET and PMOSFET lifetime factors were found to obey 4/ftcise and 10 / f tfall respectively. Typically, the NMOSFET and PMOSFET speed degradation factors are 1/4 and 1/2, respectively, with saturation region drain current as the monitor, while for a 100 MHz operating frequency and for an input rise time of 0.35 ns, the NMOSFET and PMOSFET time factors are 120 and 300, respectively.

Original languageEnglish
Pages (from-to)253-262
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Volume29
Issue number3
DOIs
StatePublished - 1 Jan 1994

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