Hot-carrier reliability design guidelines for CMOS logic circuits

Khandker N. Quader*, Eric R. Minami, Wei Jen Huang, Ping K. Ko, Chen-Ming Hu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

We present generalized hot-carrier reliability design rules that translate device-level degradation rate to CMOS circuit lifetime. The design rules can roughly predict CMOS circuit degradation during the initial design and can aid reliability engineers to quickly estimate the overall product hot-carrier reliability.

Original languageEnglish
Title of host publicationProceedings of the Custom Integrated Circuits Conference
PublisherPubl by IEEE
ISBN (Print)0780308263
DOIs
StatePublished - 1 Jan 1993
EventProceedings of the IEEE 1993 Custom Integrated Circuits Conference - San Diego, CA, USA
Duration: 9 May 199312 May 1993

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Conference

ConferenceProceedings of the IEEE 1993 Custom Integrated Circuits Conference
CitySan Diego, CA, USA
Period9/05/9312/05/93

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