Hot-carrier induced degradation of critical paths modeled by rule-based analysis

Scott B. Kuusinen*, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalConference article

1 Scopus citations

Abstract

An implementation of simple hot carrier rules is presented with the intent of providing insight into reliability problems as early in the design process as possible. To that end, these rules have been incorporated into BERT, a circuit reliability simulator, using a timing simulator as the simulation engine. This allows for quick estimation of problem points in the critical path of large circuits. Furthermore, by exploiting the inverting property of CMOS circuitry, it is possible to remove some of the estimation problems that can arise from false paths. By separating analysis into rising and falling waveforms, and partitioning the circuit into channel connected components, it is possible to prevent analysts of clearly impossible paths.

Original languageEnglish
Pages (from-to)69-72
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
DOIs
StatePublished - 1 Jan 1995
EventProceedings of the 1995 17th Annual Custom Integrated Circuits Conference - Santa Clara, CA, USA
Duration: 1 May 19954 May 1995

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