Highly scaled (Lg ∼ 56 nm) gate-last Si tunnel field-effect transistors with ION > 100 μa/μm

Wei Yip Loh*, Kanghoon Jeon, Chang Yong Kang, Jungwoo Oh, Tsu Jae King Liu, Hsing Huang Tseng, Wade Xiong, Prashant Majhi, Raj Jammy, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

14 Scopus citations

Abstract

Planar band-to-band tunneling FETs (TFETs) have been fabricated on silicon-on-insulator (SOI) substrates using conventional CMOS technologies with a highly scaled sub-60 nm gate length (effective gate length [Lg] ∼ 40 nm due to an overlap between the source and gate) and different anneal sequences. The optimal anneal sequence including spike and flash annealing resulted in a drive ON current (ION)) > 100 μA/μm with ION/IOFF > 105 at a drain bias of -1 V. The devices exhibited negative differential resistance and non-linear subthreshold temperature dependencies, consistent with the band-to-band tunneling mechanism. Simulations using a 2-D TCAD simulator, MEDICI, agreed with experimental data, demonstrating the possibility of Si tunnel transistors in logic applications.

Original languageEnglish
Pages (from-to)22-27
Number of pages6
JournalSolid-State Electronics
Volume65-66
Issue number1
DOIs
StatePublished - 1 Nov 2011

Keywords

  • Band-to-band tunneling
  • Gated p-i-n diode
  • High-k dielectric
  • Kane's model
  • Subthreshold swing
  • Tunnel field-effect transistor

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