Highly linear 100 MHz CMOS programmable gain amplifiers

Cheng Chung Hsu, Jieh-Tsorng Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Digitally programmable gain amplifiers (PGAs) are designed by using the current-mode technique to achieve constant bandwidth and high linearity. A new current amplifier and MOS switch arrays are proposed to realize the PGAs. Simulation results show that, implemented in a standard 0.35 μm CMOS technology, the amplifier exhibits a total harmonic distortion of lower than -60 dB for an 80 MHz differential output with 1.6 V peak-to-peak voltage. Dissipating 22 mW from a 3.3 V supply, a single-stage PGA can have a voltage gain varying from 0 dB to 20 dB while maintaining a constant bandwidth of 100 MHz driving 2 pF capacitive loads.

Original languageEnglish
Title of host publicationISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Pages647-650
Number of pages4
DOIs
StatePublished - 1 Dec 2001
Event2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 - Sydney, NSW, Australia
Duration: 6 May 20019 May 2001

Publication series

NameISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Volume1

Conference

Conference2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
CountryAustralia
CitySydney, NSW
Period6/05/019/05/01

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    Hsu, C. C., & Wu, J-T. (2001). Highly linear 100 MHz CMOS programmable gain amplifiers. In ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings (pp. 647-650). [921939] (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; Vol. 1). https://doi.org/10.1109/ISCAS.2001.921939