High-voltage-tolerant ESD clamp circuit with low standby leakage in nanoscale CMOS process

Ming-Dou Ker*, Chun Yu Lin

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

25 Scopus citations

Abstract

For system-on-chip applications with mixed-voltage I/O interfaces, I/O circuits with low-voltage devices must drive or receive high-voltage signals to communicate with other circuit blocks. With the consideration of low standby leakage in nanoscale CMOS processes, a new 2 × VDD -tolerant electrostatic discharge (ESD) clamp circuit by using only 1 ×V DD devices was presented in this paper. The new ESD clamp circuit had a high-voltage-tolerant ESD detection circuit to improve the turn-on efficiency of an ESD clamp device, which consisted of a silicon-controlled rectifier (SCR) with a diode in series. This design had successfully been verified in a 65-nm CMOS process. The leakage current of this ESD clamp circuit under normal circuit operating condition was only on the order of 100 nA. The test patterns with 25- and 50- \mu\hbox{m} SCR-based ESD clamp devices can achieve 2.6- and 4.8-kV human-body-model ESD robustness, respectively. Such high-voltage-tolerant ESD clamp circuits, by using only low-voltage devices with very low standby leakage current and high ESD robustness, were very suitable for mixed-voltage I/O interfaces in nanoscale CMOS processes.

Original languageEnglish
Article number5467173
Pages (from-to)1636-1641
Number of pages6
JournalIEEE Transactions on Electron Devices
Volume57
Issue number7
DOIs
StatePublished - 1 Jul 2010

Keywords

  • Electrostatic discharge (ESD)
  • low-voltage CMOS
  • mixed-voltage I/O
  • power-rail ESD clamp circuit
  • silicon-controlled rectifier (SCR)

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