High voltage lateral 4H-SiC JFETs on a semi-insulating substrate

Chih Fang Huang*, Cheng Li Kan, Tian-Li Wu, Meng Chia Lee, Yo Zthu Liu, Kung Yen Lee, Feng Zhao

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Because of the superior material properties, silicon carbide (SiC) devices have drawn considerable attention in high power and high temperature applications. Promising performance has been demonstrated on both vertical and lateral devices [1] - [3]. In this paper, we report the performance of high voltage lateral 4H-SiC JFETs built on a semi-insulating substrate. The drift region design is based on charge compensation of the n-and p-type materials. The best achieved breakdown voltage is 3510 V, which is the highest value ever published for SiC lateral switching devices. Ron, sp is 390 mΩ-cm2, resulting in a BV2/Ron, sp of 32 MW/cm2.

Original languageEnglish
Title of host publication67th Device Research Conference, DRC 2009
Pages275-276
Number of pages2
DOIs
StatePublished - 11 Dec 2009
Event67th Device Research Conference, DRC 2009 - University Park, PA, United States
Duration: 22 Jun 200924 Jun 2009

Publication series

NameDevice Research Conference - Conference Digest, DRC
ISSN (Print)1548-3770

Conference

Conference67th Device Research Conference, DRC 2009
CountryUnited States
CityUniversity Park, PA
Period22/06/0924/06/09

Fingerprint Dive into the research topics of 'High voltage lateral 4H-SiC JFETs on a semi-insulating substrate'. Together they form a unique fingerprint.

Cite this