High V th enhancement mode GaN power devices with high I D, max using hybrid ferroelectric charge trap gate stack

C. H. Wu, S. C. Liu, C. K. Huang, Y. C. Chiu, P. C. Han, P. C. Chang, F. Lumbantoruan, C. A. Lin, Y. K. Lin, C. Y. Chang, Chenming Hu, Hiroshi Iwai, Edward Yi Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

In this work, we demonstrate a new concept for realizing high threshold voltage (V th ) E-mode GaN power devices with high maximum drain current (I D, max ). A gate stack ferroelectric blocking film with charge trap layer, achieved a large positive shift of V th . The E-mode GaN MIS-HEMTs with high V th of 6 V shows I D, max 720 mA/mm. The breakdown voltage is above 1100 V.

Original languageEnglish
Title of host publication2017 Symposium on VLSI Technology, VLSI Technology 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
PagesT60-T61
ISBN (Electronic)9784863486058
DOIs
StatePublished - 31 Jul 2017
Event37th Symposium on VLSI Technology, VLSI Technology 2017 - Kyoto, Japan
Duration: 5 Jun 20178 Jun 2017

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Conference

Conference37th Symposium on VLSI Technology, VLSI Technology 2017
CountryJapan
CityKyoto
Period5/06/178/06/17

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    Wu, C. H., Liu, S. C., Huang, C. K., Chiu, Y. C., Han, P. C., Chang, P. C., Lumbantoruan, F., Lin, C. A., Lin, Y. K., Chang, C. Y., Hu, C., Iwai, H., & Chang, E. Y. (2017). High V th enhancement mode GaN power devices with high I D, max using hybrid ferroelectric charge trap gate stack. In 2017 Symposium on VLSI Technology, VLSI Technology 2017 (pp. T60-T61). [7998201] (Digest of Technical Papers - Symposium on VLSI Technology). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSIT.2017.7998201