As the industry continues to scale devices to meet the various system-on-a-chip applications in the future, several types of transistor designs from planar and vertical single-gate, double-gate, and multigate devices are emerging, as are several options in silicon starting material (bulk CZ, epi, blanket SOI, and selective/patterned SOI wafers) [1-7]. Although planar single-gate device scaling has been demonstrated down to a gate length (Lg) of 6nm, the end of the roadmap for planar single-gate CMOS seems to be drawing nearer as the industry increases research activities in double-gate and multigate CMOS devices . Multiple device roadmaps that depend on specific applications are also emerging and both logic and memory devices will migrate from planar structures to vertical structures.
|Specialist publication||Solid State Technology|
|State||Published - Jun 2003|