Abstract
In this letter we propose a high-throughput VLSI architecture design for H.264 high-profile context-based adaptive binary arithmatic coding (HP CABAC) decoding for HDTV applications. To speed up the inherent sequential CABAC decoding, we eliminate the bottleneck by proposing a look-ahead decision parsing technique on the grouped context table with cache registers, which reduces 62% of cycle count on average as compared with the original CABAC decoding. In addition, the proposed design supports the macroblock adaptive frame field coding tools in H.264 main profile coding and 8 × 8 transform in H.264 high-profile coding. It achieves the real-time processing for H.264 CABAC decoding up to L4.1@30 frames/s with maximum 60 Mbits/s when operating at 105 MHz.
Original language | English |
---|---|
Article number | 4812002 |
Pages (from-to) | 1395-1399 |
Number of pages | 5 |
Journal | IEEE Transactions on Circuits and Systems for Video Technology |
Volume | 19 |
Issue number | 9 |
DOIs | |
State | Published - 1 Sep 2009 |
Keywords
- Context-based adaptive binary arithmatic coding (CABAC)
- H.264
- HDTV
- Video coding