The paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well known LZ77 algorithm. The architecture mainly consists of three units, namely, content addressable memory, match-logic unit, and output-stage unit. The content-address-memory unit generates a set of hits signals which identify those positions whose symbols in a specified window are the same as the input symbol. These hits signals are then passed to the match-logic unit which determines both match length and location to form the kernel of compressed data. These two items are then passed to the output-stage unit for packetisation before being sent out. Simulation results show that, based on a 0.8 μm CMOS process technology, a clock speed of up to 50 MHz can be achieved for a VLSI design containing a 2K buffer size. This implies that the developing data compressor chip can handle many real-life applications, such as in high-speed data storage and networking systems.