This paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well-known LZ77 algorithm. The architecture mainly consists of three units, namely content addressable memory, match logic, and output stage. The content address memory generates a set of hit signals which identify those positions whose symbols in a specified window are the same as input symbol. These hits signals are then passed to the match logic which determines one matched stream and its match length and location in the window to form the kernel of compressed data. These two items are then passed to the output stage for packetization before sent out. By trading off hardware complexity and compression ratio, 2KB window size and adjustable maximum match length are considered in our proto-type VLSI chip. Simulation results show that, based on a 0.8μm CMOS process technology, clock speed up to 50MHz can be achieved. This implies that the developing data compressor chip can handle many real-life applications such as in video coding and high-speed data storage systems.
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - 1 Dec 1994|
|Event||Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England|
Duration: 30 May 1994 → 2 Jun 1994