Radar technology and its developments have been important issues for decades. With the growth of semiconductor processing technology, the development of circuit design related to THz technology has gradually been noted such as imaging radar system. However, there are ultra-long series in the application of wideband radar system with high sampling rate. While realizing the ultra-long FFT, it would introduce some design challenges. On the other hand, it needs to achieve a high throughput rate to meet the requirement of real-time processing. In this paper, we implement a 4-parallel 64K-point FFT hardware architecture based on 2-epoch FFT algorithm. With the proposed middle twiddle factor generator, we can reduce a large number of storages for twiddle factor coefficients, so that the area of ROM can be reduced. We implement this work in TSMC 90 nm CMOS technology with high- Vt standard cell library and the total gate counts are around 3974.1k. The maximum operating frequency of the system is 390 MHz. When operating at the maximum operating frequency, the throughput reaches 1.57 GS/s and it consumes 0.2811 W (@0.9 V).