High-speed VLSI pipelined processor design for lossless image data compression

Wai-Chi Fang, Bing J. Sheu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

An efficient VLSI pipelined processor design for high-speed lossless compression based on "Rice algorithm" has been developed to meet the increasing strong demands on high-volume/high-speed image data communication and storage. The Rice algorithm is an adaptive lossless coding scheme that provides near-optimal performance over a broad range of data entropies. The Rice algorithm is also an efficiently implementable scheme for VLSI realization. A VLSI pipelined architecture was developed to allow compact implementation of a single-chip VLSI compressor. This lossless compressor is named PSI14,K+ since it implements an advanced version of the Rice's universal noiseless coding method called PSI14,K+. The chip layout was generated for a 1.0- micron CMOS technology. It occupies a compact chip area of 5.1 × 5.3 mm2, with 49,000 transistors, 57 input/output pads, and 6 power/ground pads. The total power dissipation is 0.4 watts at the 40 MHz system clock with a 50% switching duty cycle. This compressor chip is mounted in a 68-pin pin-grid-array package. It can operate up to 40 Mpixels/sec. The potential applications of the proposed lossless compressor include database management systems, scientific instruments, CAE workstations, desktop computing machines, and the data systems that require highspeed compression without fidelity loss.

Original languageEnglish
Title of host publicationWorkshop on VLSI Signal Processing 1992
EditorsWojtek Przytula, Kung Yao, Rajeev Jain, Jan Rabaey
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages215-224
Number of pages10
ISBN (Electronic)0780308115, 9780780308114
DOIs
StatePublished - 1 Jan 1992
Event6th IEEE Workshop on VLSI Signal Processing - Los Angeles, United States
Duration: 28 Oct 199230 Oct 1992

Publication series

NameWorkshop on VLSI Signal Processing 1992

Conference

Conference6th IEEE Workshop on VLSI Signal Processing
CountryUnited States
CityLos Angeles
Period28/10/9230/10/92

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    Fang, W-C., & Sheu, B. J. (1992). High-speed VLSI pipelined processor design for lossless image data compression. In W. Przytula, K. Yao, R. Jain, & J. Rabaey (Eds.), Workshop on VLSI Signal Processing 1992 (pp. 215-224). [641054] (Workshop on VLSI Signal Processing 1992). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSISP.1992.641054